Cyient Semiconductors, a fast-growing custom silicon company based in Hyderabad, and MIPS, a global leader in RISC-V processor IP, today announced a strategic collaboration to develop domain-optimized ASIC (application-specific integrated circuit) and ASSP (application-specific standard product) solutions that leverage the MIPS Atlas portfolio of advanced, efficient processor IP.
The partnership will focus on enabling real-time, safety-critical applications, power delivery, and compute efficiency in demanding platforms for automotive, industrial, and data center markets. Motor Control & Data Center Power Delivery are focal platforms to leverage Cyient's Analog Mixed Signal capabilities and MIPS Atlas CPU IP.
“As compute systems scale from cloud to the edge, intelligent power delivery is emerging as a key enabler of performance and efficiency,” said Suman Narayan, CEO of Cyient Semiconductors. “Our collaboration with MIPS allows us to bring together embedded intelligence and advanced power architectures in custom silicon platforms built on a scalable, open foundation. Together, we are designing tomorrow's semiconductors — purpose-built for a more connected and power-efficient world.”
Demand for software defined vehicles, data center infrastructure, and industrial automation is driving growth for custom silicon. Customers can build advanced, differentiated solutions that are easy to program using MIPS advanced processor IP, based on the open RISC-V instruction set architecture, combined with Cyient intelligent power and mixed-signal design expertise.
Targeted applications include motor drive control, intelligent power management, power delivery management, and safety-critical applications, offered as ASSP or ASIC platforms. OEMs and system integrators will benefit from faster time-to-market, avoiding proprietary lock-ins, and optimized platform cost.